CPC G06F 11/0778 (2013.01) [G06F 11/0757 (2013.01); G06F 12/0882 (2013.01); G06F 13/1673 (2013.01); G11C 7/1039 (2013.01); G11C 7/1087 (2013.01); G11C 11/4074 (2013.01); G11C 11/4093 (2013.01)] | 20 Claims |
1. A non-volatile memory device comprising:
a memory cell array including a plurality of memory cells, each memory cell configured to be programmed to one state of a plurality of states;
a page buffer circuit including a plurality of page buffers, each page buffer configured to store received data as state data indicating a target state of a corresponding memory cell of the plurality of memory cells, the page buffer circuit being configured to perform a state data reordering operation of changing a first state data order indicating reference mapping between a plurality of data values of the state data and the plurality of states into a second state data order during at least one verification period among a plurality of verification period in which a verification operation is performed on selected memory cells of the plurality of memory cells; and
a reordering control circuit configured to control the page buffer circuit to perform the state data reordering operation simultaneously with the verification read operation.
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