US 11,989,081 B2
Method for CXL fallback in a CXL system
Isaac Q. Wang, Austin, TX (US); Stuart Allen Berke, Austin, TX (US); and Jordan Chin, Austin, TX (US)
Assigned to Dell Products L.P., Round Rock, TX (US)
Filed by DELL PRODUCTS L.P., Round Rock, TX (US)
Filed on Jul. 19, 2022, as Appl. No. 17/868,427.
Application 17/868,427 is a continuation in part of application No. 17/863,540, filed on Jul. 13, 2022.
Prior Publication US 2024/0028438 A1, Jan. 25, 2024
Int. Cl. G06F 11/00 (2006.01); G06F 9/448 (2018.01); G06F 11/07 (2006.01); G06F 13/42 (2006.01)
CPC G06F 11/0772 (2013.01) [G06F 9/4498 (2018.02); G06F 11/0778 (2013.01); G06F 13/4221 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An information handling system, comprising:
a processor; and
a compute express link (CXL) device coupled to the processor by a peripheral component interface-express (PCIe)/CXL link;
wherein the processor is configured to initiate a link training on the PCIe/CXL link, to determine that the PCIe/CXL link failed to train to a first data rate, to train the PCIe/CXL link to a second data rate in response to determining that the PCIe/CXL link failed to train to the first data rate, and to operate the CXL device in a PCIe mode in response to training the PCIe/CXL link to the second data rate.