US 11,989,078 B2
Vehicle control device and method thereof
Yu-Long Wang, Hsinchu (TW); Nan-Hsiung Tseng, Hsinchu (TW); and Yi-Lun Cheng, Hsinchu (TW)
Assigned to INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, Hsinchu (TW)
Filed by INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, Hsinchu (TW)
Filed on Jun. 7, 2022, as Appl. No. 17/833,935.
Claims priority of provisional application 63/250,291, filed on Sep. 30, 2021.
Prior Publication US 2023/0100219 A1, Mar. 30, 2023
Int. Cl. G06F 11/00 (2006.01); B60R 16/02 (2006.01); G06F 1/28 (2006.01); G06F 11/07 (2006.01); G06F 11/14 (2006.01)
CPC G06F 11/00 (2013.01) [B60R 16/02 (2013.01); G06F 1/28 (2013.01); G06F 11/0739 (2013.01); G06F 11/0757 (2013.01); G06F 11/1441 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A vehicle control device, comprising:
a power management module;
a master processor and a slave processor simultaneously receiving, monitoring or processing at least one signal of a vehicle, wherein the master processor is respectively connected to the power management module and the slave processor, wherein the power management module monitors the master processor via a first watchdog signal, and the master processor monitors the slave processor via a second watchdog signal, wherein when the power management module sends the first watchdog signal to the master processor, and the master processor does not respond to the power management module with a message in response to the first watchdog signal, the power management module sends a first reset signal to the master processor for reset, and wherein when the master processor sends the second watchdog signal to the slave processor, and the slave processor does not respond to the master processor with a message in response to the second watchdog signal, the master processor sends a second reset signal to the slave processor for reset; and
a forced wake-up module respectively connected to the master processor and the slave processor, wherein when the power management module is abnormal or both the master processor and the slave processor are abnormal, the forced wake-up module outputs a high level signal to a reset terminal of the master processor and a reset terminal of the slave processor to forcibly wake up the master processor and the slave processor.