| CPC G06F 1/3296 (2013.01) [G06F 1/3206 (2013.01); G06F 1/3203 (2013.01)] | 20 Claims |
|
1. A management circuit coupled to a plurality of processor cores for performing current suppression, comprising:
a detection circuit operative to:
receive an activity signal from each processor core, the activity signal indicating a current index proportional to current consumption of the processor core in a given time period, wherein the current index corresponds to a sum of respective values assigned to respective opcodes executed or to be executed by the processor core in the given time period; and
estimate a total current consumed by the plurality of processor cores based on activity signals of the processor cores; and
a throttle signal generator operative to assert or de-assert throttle signals to the plurality of processor cores, one processor core at a time, based on one or more metrics calculated from the total current.
|