CPC G06F 1/28 (2013.01) [G06F 1/3206 (2013.01); G06F 1/3243 (2013.01); G06F 1/3287 (2013.01); G06F 9/30014 (2013.01); G06F 9/30018 (2013.01); G06F 9/30036 (2013.01); G06F 9/30072 (2013.01); G06F 9/30109 (2013.01); G06F 9/30112 (2013.01); G06F 9/3013 (2013.01); G06F 9/3887 (2013.01); G06F 13/26 (2013.01); G06F 9/3004 (2013.01); G06F 9/30105 (2013.01); G06F 9/3016 (2013.01); Y02D 10/00 (2018.01)] | 20 Claims |
1. A processor device comprising:
a vector data path that includes a set of vector lanes;
a register configured to store a set of data that specifies whether a subset of the set of vector lanes is powered on;
a decoder coupled to the register and the vector data path and configured to cause the subset of the set of vector lanes to be powered on based on the set of data stored in the register; and
a memory coupled to the decoder, wherein the processor device is configured to:
receive an interrupt;
based on the interrupt, copy the set of data from the register to the memory; and
service the interrupt; and
based on completion of servicing of the interrupt, copy the set of data from the memory to the register.
|