US 11,989,072 B2
Controlling the number of powered vector lanes via a register field
Timothy David Anderson, University Park, TX (US); and Duc Quang Bui, Grand Prairie, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Jun. 13, 2022, as Appl. No. 17/838,368.
Application 17/838,368 is a continuation of application No. 16/983,451, filed on Aug. 3, 2020, granted, now 11,360,536.
Application 16/983,451 is a continuation of application No. 15/638,407, filed on Jun. 30, 2017, granted, now 10,732,689, issued on Aug. 4, 2020.
Application 15/638,407 is a continuation in part of application No. 14/326,928, filed on Jul. 9, 2014, granted, now 10,175,981, issued on Jan. 8, 2019.
Claims priority of provisional application 61/844,124, filed on Jul. 9, 2013.
Prior Publication US 2022/0308648 A1, Sep. 29, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/3206 (2019.01); G06F 1/28 (2006.01); G06F 1/3234 (2019.01); G06F 1/3287 (2019.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 13/26 (2006.01)
CPC G06F 1/28 (2013.01) [G06F 1/3206 (2013.01); G06F 1/3243 (2013.01); G06F 1/3287 (2013.01); G06F 9/30014 (2013.01); G06F 9/30018 (2013.01); G06F 9/30036 (2013.01); G06F 9/30072 (2013.01); G06F 9/30109 (2013.01); G06F 9/30112 (2013.01); G06F 9/3013 (2013.01); G06F 9/3887 (2013.01); G06F 13/26 (2013.01); G06F 9/3004 (2013.01); G06F 9/30105 (2013.01); G06F 9/3016 (2013.01); Y02D 10/00 (2018.01)] 20 Claims
OG exemplary drawing
 
1. A processor device comprising:
a vector data path that includes a set of vector lanes;
a register configured to store a set of data that specifies whether a subset of the set of vector lanes is powered on;
a decoder coupled to the register and the vector data path and configured to cause the subset of the set of vector lanes to be powered on based on the set of data stored in the register; and
a memory coupled to the decoder, wherein the processor device is configured to:
receive an interrupt;
based on the interrupt, copy the set of data from the register to the memory; and
service the interrupt; and
based on completion of servicing of the interrupt, copy the set of data from the memory to the register.