US 11,989,050 B2
Multi-chiplet clock delay compensation
Anwar Kashem, Boxborough, MA (US); Craig Daniel Eaton, Austin, TX (US); Pouya Najafi Ashtiani, Munich (DE); and Deepesh John, Austin, TX (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Dec. 29, 2021, as Appl. No. 17/565,382.
Prior Publication US 2023/0205252 A1, Jun. 29, 2023
Int. Cl. G06F 1/08 (2006.01); H03K 5/22 (2006.01); H03K 5/00 (2006.01)
CPC G06F 1/08 (2013.01) [H03K 5/22 (2013.01); H03K 2005/00286 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for clock delay compensation in a multiple chiplet system, comprising:
distributing, by a clock generator, a clock signal across distribution trees of respective chiplets in the multiple chiplet system;
measuring, by a phase detector, a respective phase measurement that is associated with a respective chiplet in the multiple chiplet system, wherein the respective phase measurement is indicative of a propagation speed of the clock signal through a plurality of paths of the distribution tree of the respective chiplet; and
for each chiplet in the multiple chiplet system:
determining, by a microcontroller, based on the respective phase measurements associated with the respective chiplet, a delay offset and local delay offsets, and
delaying, based on the delay offset and on the local delay offsets, propagation of the clock signal through the distribution tree of the respective chiplet using a delay unit associated with the respective chiplet.