US 11,988,926 B2
Display apparatus and electronic device
Susumu Kawashima, Atsugi (JP); and Naoto Kusumoto, Isehara (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Appl. No. 17/612,384
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
PCT Filed May 18, 2020, PCT No. PCT/IB2020/054663
§ 371(c)(1), (2) Date Nov. 18, 2021,
PCT Pub. No. WO2020/240329, PCT Pub. Date Dec. 3, 2020.
Claims priority of application No. 2019-101319 (JP), filed on May 30, 2019.
Prior Publication US 2022/0252949 A1, Aug. 11, 2022
Int. Cl. G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); H01L 27/12 (2006.01)
CPC G02F 1/136213 (2013.01) [G02F 1/13624 (2013.01); G02F 1/1368 (2013.01); H01L 27/1255 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A display apparatus comprising, in a pixel, a first capacitor, a second capacitor, and a display element,
wherein the first capacitor and the second capacitor are electrically connected to the display element,
wherein the first capacitor comprises a structure in which a first conductive layer, a first dielectric layer, and a second conductive layer are stacked in this order,
wherein the second capacitor comprises a structure in which the second conductive layer, a second dielectric layer, and a third conductive layer are stacked in this order,
wherein the first capacitor and the second capacitor comprise a region where the first capacitor and the second capacitor overlap with each other,
wherein a potential of the first conductive layer is configured to be different from a potential of the third conductive layer,
wherein the pixel further comprises a first transistor, a second transistor, and a third transistor,
wherein one of a source and a drain of the first transistor is electrically connected to the second conductive layer, and
wherein one of a source and a drain of the second transistor and one of a source and a drain of the third transistor are electrically connected to the third conductive layer.