US 11,988,720 B2
Semiconductor device and battery pack
Kei Takahashi, Isehara (JP); Takayuki Ikeda, Atsugi (JP); Ryota Tajima, Isehara (JP); Mayumi Mikami, Atsugi (JP); Yohei Momma, Isehara (JP); Munehiro Kozuma, Atsugi (JP); and Takanori Matsuzaki, Atsugi (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Appl. No. 17/312,475
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
PCT Filed Dec. 13, 2019, PCT No. PCT/IB2019/060740
§ 371(c)(1), (2) Date Jun. 10, 2021,
PCT Pub. No. WO2020/128743, PCT Pub. Date Jun. 25, 2020.
Claims priority of application No. 2018-238529 (JP), filed on Dec. 20, 2018; and application No. 2019-123810 (JP), filed on Jul. 2, 2019.
Prior Publication US 2022/0052387 A1, Feb. 17, 2022
Int. Cl. G01R 31/392 (2019.01); H01M 10/44 (2006.01); H01M 10/48 (2006.01); H02J 7/00 (2006.01); H01L 29/786 (2006.01)
CPC G01R 31/392 (2019.01) [H01M 10/44 (2013.01); H01M 10/48 (2013.01); H02J 7/005 (2020.01); H01L 29/7869 (2013.01); H01M 2220/20 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A semiconductor device comprising a first circuit and a second circuit,
wherein the first circuit comprises a power gauge and an anomalous current detection circuit,
wherein the power gauge comprises a current divider circuit and an integrator circuit,
wherein the anomalous current detection circuit comprises a first memory, a second memory, and a first comparator,
wherein the integrator circuit is configured to convert a detection current detected at the current divider circuit into a detection voltage by integrating the detection current,
wherein the anomalous current detection circuit is configured to be supplied with the detection voltage, a first signal at a first time, and a second signal at a second time,
wherein the anomalous current detection circuit is configured to store the detection voltage at the first time in the first memory using the first signal,
wherein the anomalous current detection circuit is configured to store the detection voltage at the second time in the second memory using the second signal, and
wherein the first comparator is configured to output a change from the detection voltage at the first time to the detection voltage at the second time as a first output signal to the second circuit.