US 11,988,711 B2
Test circuit and test method
Po-Lin Chen, Hsinchu (TW); and Chun-Teng Chen, Hsinchu (TW)
Assigned to REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed by REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed on Feb. 27, 2023, as Appl. No. 18/175,471.
Claims priority of application No. 111108789 (TW), filed on Mar. 10, 2022.
Prior Publication US 2023/0288478 A1, Sep. 14, 2023
Int. Cl. G01R 31/3177 (2006.01); G01R 31/3185 (2006.01)
CPC G01R 31/3177 (2013.01) [G01R 31/318536 (2013.01); G01R 31/318541 (2013.01); G01R 31/318544 (2013.01); G01R 31/318594 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A test circuit, configured to test a circuit under test, comprising:
a first wrapper chain, configured to shift in a test pattern according to a first clock in a scan in phase; and
a scan chain, coupled to the first wrapper chain via a first logic combination of the circuit under test,
wherein the first wrapper chain is further configured to transmit the test pattern to the scan chain via the first logic combination according to a second clock in a capture phase,
wherein the first wrapper chain comprises:
a first wrapper cell, configured to sequentially shift in a first bit and a second bit of the test pattern in the scan in phase;
a second wrapper cell, configured to shift in the first bit of the test pattern from the first wrapper cell in the scan in phase; and
a first asynchronous register, coupled between the first wrapper cell and the second wrapper cell, configured to conduct an output terminal of the first wrapper cell to an input terminal of the second wrapper cell in the scan in phase, and latch the input terminal of the second wrapper cell in the capture phase.