US 11,988,704 B2
Test circuits and semiconductor test methods
ChihCheng Liu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Appl. No. 17/431,232
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
PCT Filed Mar. 9, 2021, PCT No. PCT/CN2021/079649
§ 371(c)(1), (2) Date Aug. 16, 2021,
PCT Pub. No. WO2021/196990, PCT Pub. Date Oct. 7, 2021.
Claims priority of application No. 202010259653.7 (CN), filed on Apr. 3, 2020.
Prior Publication US 2023/0057528 A1, Feb. 23, 2023
Int. Cl. G01R 31/14 (2006.01); G01R 31/26 (2020.01)
CPC G01R 31/14 (2013.01) [G01R 31/2642 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A test circuit, comprising:
M test units, each test unit having a first terminal and a second terminal, the first terminal of each test unit being connected to a power wire, the second terminal of each test unit being connected to a ground wire, M being a positive integer;
each test unit comprises a time dependent dielectric breakdown (TDDB) test component, a switch, and a control circuit, wherein each TDDB test component has a first resistance value before being broken down, each TDDB test component has a second resistance value after being broken down, the first resistance value is greater than the second resistance value, a first terminal of each TDDB test component is the first terminal of the test unit and a second terminal of each TDDB test component is connected to a first terminal of each switch, a second terminal of each switch is the second terminal of the test unit, and the first terminal of each switch is connected to a control terminal of each switch through each control circuit.