CPC G01N 21/9501 (2013.01) [G06T 7/0004 (2013.01); G06T 7/11 (2017.01); G01N 2021/8864 (2013.01); G06T 2207/30148 (2013.01)] | 20 Claims |
1. A computerized system of assisting defect detection on a semiconductor specimen, the system comprising a processing and memory circuitry (PMC) configured to:
obtain a first map informative of multiple care areas (CAs) to be inspected on a die of the semiconductor specimen;
create a plurality of bounding rectangles (BRs) enclosing the multiple CAs; and
compact the plurality of BRs to a set of compacted rectangles to meet a predefined inspection capacity while attempting to minimize a non-CA area enclosed by the set of compacted rectangles, giving rise to a second map informative of the set of compacted rectangles, wherein the compacting comprises:
constructing an R-tree structure comprising a bottom layer and one or more upper layers, the bottom layer comprising a plurality of leaf nodes representative of the plurality of BRs, each of the one or more upper layers comprising one or more non-leaf nodes, each given non-leaf node representative of a compacted rectangle enclosing one or more rectangles represented by one or more child nodes of the given non-leaf node, and
selecting a set of nodes from the leaf nodes and the non-leaf nodes of the R-tree structure based on the predefined inspection capacity, the set of nodes representative of the set of compacted rectangles;
wherein the second map is usable for filtering a defect map indicative of defect candidate distribution on the die.
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