US 6,680,516 C1 (12,602nd)
Controlled thickness gate stack
Alain Blosse, Belmont, CA (US); and Krishnaswamy Ramkumar, San Jose, CA (US)
Filed by Alain Blosse, Belmont, CA (US); and Krishnaswamy Ramkumar, San Jose, CA (US)
Assigned to Monterey Research, LLC
Reexamination Request No. 90/015,213, Mar. 20, 2023.
Reexamination Certificate for Patent 6,680,516, issued Jan. 20, 2004, Appl. No. 10/313,267, Dec. 6, 2002.
Ex Parte Reexamination Certificate issued on May 17, 2024.
Int. Cl. H01L 21/768 (2006.01); H01L 29/423 (2006.01)
CPC H01L 21/76897 (2013.01) [H01L 29/42372 (2013.01)]
OG exemplary drawing
AS A RESULT OF REEXAMINATION, IT HAS BEEN DETERMINED THAT:
The patentability of claims 5-8 and 10-11 is confirmed.
Claims 1-4, 9, and 12-20 were not reexamined.
5. A semiconductor structure, comprising;
a semiconductor substrate,
a gate layer, on the semiconductor substrate,
a metallic layer, on the gate layer,
an etch-stop layer, on the metallic layer,
an insulating layer, on the etch-stop layer, and on the substrate, and
a via, through the insulating layer, on the substrate,
wherein an area of contact between the via and the substrate has a via width,
the via width is at most 0.12 micron,
a distance between the substrate and a top of the etch-stop layer has a gate stack height, and
the gate stack height is at most 2700 angstroms.