US RE49,535 E1
Memory interface with selectable connections for input receiver circuits based on operating mode
Young Chul Cho, Seongnam-si (KR); Jung Bae Lee, Seongnam-si (KR); and Jung Hwan Choi, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Apr. 3, 2020, as Appl. No. 16/839,573.
Application 15/416,565 is a continuation of application No. 14/818,586, filed on Aug. 5, 2015, granted, now 9,575,923, issued on Feb. 21, 2017.
Application 14/818,586 is a continuation of application No. 14/093,916, filed on Dec. 2, 2013, granted, now 9,130,557, issued on Sep. 8, 2015.
Application 16/839,573 is a reissue of application No. 15/416,565, filed on Jan. 26, 2017, granted, now 9,934,169, issued on Apr. 3, 2018.
Claims priority of provisional application 61/732,589, filed on Dec. 3, 2012.
Claims priority of application No. 10-2013-0028039 (KR), filed on Mar. 15, 2013.
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/16 (2006.01); G06F 13/40 (2006.01); G06F 1/32 (2019.01); G05F 1/625 (2006.01); G06F 1/3287 (2019.01); G06F 13/42 (2006.01); H03K 19/00 (2006.01)
CPC G06F 13/16 (2013.01) [G05F 1/625 (2013.01); G06F 1/3287 (2013.01); G06F 13/4068 (2013.01); G06F 13/4221 (2013.01); H03K 19/0005 (2013.01); Y02D 10/00 (2018.01)] 30 Claims
OG exemplary drawing
 
[ 22. An input/output interface circuit for a memory controller, the input/output interface circuit comprising:
a mode register configured to store an operation mode of the memory controller, the operation mode indicating one of a first operation mode and a second operation mode;
an input receiver block connected with an input/output pad, the input receiver block including a first input receiver circuit and a second input receiver circuit, and one of the first input receiver circuit and the second input receiver circuit being selectively connected to the input/output pad according to the operation mode and receiving an input data signal;
a first on-die-termination (ODT) circuit connected between the input/output pad and a supply node at a supply voltage level VDDQ, and selectively turned on or turned off according to the operation mode; and
a second on-die-termination (ODT) circuit connected between the input/output pad and a ground node at a ground voltage level VSSQ, and selectively turned on or turned off according to the operation mode,
wherein, when the operation mode indicates the first operation mode, the first input receiver circuit is connected to the input/output pad and receives the input data signal while the first ODT circuit is turned on, and when the operation mode indicates the second operation mode, the second input receiver circuit is connected to the input/output pad and receives the input data signal while the second ODT circuit is turned on.]