US 11,659,780 B2
Phase change memory structure with efficient heating system
Injo Ok, Loudonville, NY (US); Alexander Reznicek, Troy, NY (US); Choonghyun Lee, Rensselaer, NY (US); and Soon-Cheon Seo, Glenmont, NY (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Mar. 5, 2019, as Appl. No. 16/293,167.
Prior Publication US 2020/0287134 A1, Sep. 10, 2020
Int. Cl. H01L 45/00 (2006.01); G11C 13/00 (2006.01)
CPC H01L 45/141 (2013.01) [G11C 13/0004 (2013.01); H01L 45/06 (2013.01); H01L 45/128 (2013.01); H01L 45/1608 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a pore-type heater having a center pore recess; and
a tapered structure formed on the pore-type heater and having a tip portion at least extending down to the center pore recess;
wherein the pore-type heater further has a per-single-heater-dedicated, non-tapered dual-walled-per-side containment layer confining volatile active material by two encapsulating adjacent non-tapered elements which are adjacent to each other, a first of the two encapsulating adjacent non-tapered elements fully encapsulating sides and a bottom region of the volatile active material and a second of the two encapsulating adjacent non-tapered elements fully encapsulating only sides of the first of the two encapsulating adjacent non-tapered elements without contacting an area of the first of the two encapsulating adjacent non-tapered materials under the bottom region and under the pore-type heater, and wherein the per-single-heater-dedicated, non-tapered dual-walled-per-side containment layer and the two encapsulating adjacent non-tapered elements are partially recessed within a metal layer inter-dispersed within a dielectric layer.