US 11,659,712 B2
Three-dimensional semiconductor memory devices
Taehee Lee, Seoul (KR); Hyunwook Kim, Seoul (KR); and Eun-jung Yang, Gunpo-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Apr. 4, 2022, as Appl. No. 17/712,225.
Application 17/712,225 is a continuation of application No. 16/732,518, filed on Jan. 2, 2020, granted, now 11,302,709.
Application 16/732,518 is a continuation of application No. 16/149,848, filed on Oct. 2, 2018, granted, now 10,553,610, issued on Feb. 4, 2020.
Claims priority of application No. 10-2018-0036678 (KR), filed on Mar. 29, 2018.
Prior Publication US 2022/0223621 A1, Jul. 14, 2022
Int. Cl. H01L 27/11582 (2017.01); H01L 27/1157 (2017.01); H01L 27/11565 (2017.01)
CPC H01L 27/11582 (2013.01) [H01L 27/1157 (2013.01); H01L 27/11565 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A three-dimensional semiconductor memory device comprising:
an electrode structure including a plurality of gate electrodes stacked in a first direction that is perpendicular to a top surface of a substrate;
a lower pattern group including a plurality of lower vertical patterns that are in a lower portion of the electrode structure and are connected to the substrate; and
an upper pattern group including a plurality of upper vertical patterns that are in an upper portion of the electrode structure,
wherein the plurality of upper vertical patterns are connected to the plurality of lower vertical patterns, respectively,
wherein a first upper vertical pattern of the plurality of upper vertical patterns is connected to a first lower vertical pattern of the plurality of lower vertical patterns, a center of a bottom surface of the first upper vertical pattern is offset in a second direction from a center of a top surface of the first lower vertical pattern, and the second direction is parallel to the top surface of the substrate, and
wherein a second upper vertical pattern of the plurality of upper vertical patterns is connected to a second lower vertical pattern of the plurality of lower vertical patterns, and a center of a bottom surface of the second upper vertical pattern is offset in an opposite direction of the second direction from a center of a top surface of the second lower vertical pattern.