US 11,659,708 B2
Memory array and method used in forming a memory array comprising strings of memory cells
John D. Hopkins, Meridian, ID (US); and Nancy M. Lomeli, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 6, 2020, as Appl. No. 17/91,420.
Prior Publication US 2022/0149061 A1, May 12, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/11582 (2017.01)
CPC H10B 41/27 (2023.02) [H10B 41/10 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] 16 Claims
OG exemplary drawing
 
1. A method used in forming a memory array comprising strings of memory cells, comprising:
forming a conductor tier comprising upper conductor material directly above and directly electrically coupled to lower conductor material, the upper and lower conductor materials comprising different compositions relative one another;
forming a stack comprising vertically-alternating first tiers and second tiers above the conductor tier, the stack comprising laterally-spaced memory-block regions, material of the first tiers being of different composition from material of the second tiers;
forming channel-material strings that extend through the first tiers and the second tiers and through the upper conductor material into the lower conductor material; and
forming intervening material laterally-between and longitudinally-along immediately-laterally-adjacent of the memory-block regions.