US 11,659,707 B2
Method of manufacturing a semiconductor structure
Ching-Chia Huang, Taipei (TW); and Wei-Ming Liao, Taoyuan (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on Mar. 22, 2022, as Appl. No. 17/655,791.
Application 17/655,791 is a division of application No. 16/792,157, filed on Feb. 14, 2020, granted, now 11,315,930.
Prior Publication US 2022/0216213 A1, Jul. 7, 2022
Int. Cl. H10B 12/00 (2023.01); H01L 23/528 (2006.01); H01L 29/49 (2006.01); H01L 29/08 (2006.01); H01L 23/532 (2006.01); H01L 21/306 (2006.01)
CPC H10B 12/34 (2023.02) [H01L 21/30604 (2013.01); H01L 23/528 (2013.01); H01L 23/53257 (2013.01); H01L 23/53271 (2013.01); H01L 29/0847 (2013.01); H01L 29/4925 (2013.01); H01L 29/4958 (2013.01); H10B 12/033 (2023.02); H10B 12/053 (2023.02); H10B 12/31 (2023.02); H10B 12/485 (2023.02); H10B 12/488 (2023.02)] 9 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor structure, comprising:
providing a substrate having an active region surrounded by an isolation layer;
forming a first trench and a second trench in the active region, and a third trench and a fourth trench in the isolation layer;
forming a bottom work-function layer in the third trench and the fourth trench, respectively;
forming a middle work-function layer on the bottom work-function layer and in the first and the second trenches;
forming a top work-function layer on the middle work-function layer; and
forming a capping layer on the top work-function layer that fills a remaining region of the first, the second, the third and the fourth trenches.