US 11,659,703 B2
Integrated circuit with embedded high-density and high-current SRAM macros
Jhon Jhy Liaw, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Feb. 26, 2021, as Appl. No. 17/187,068.
Prior Publication US 2022/0278110 A1, Sep. 1, 2022
Int. Cl. H01L 27/11 (2006.01); H01L 23/528 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 29/49 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/417 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 21/8238 (2006.01); G11C 11/419 (2006.01)
CPC H01L 27/1108 (2013.01) [G11C 11/419 (2013.01); H01L 21/28088 (2013.01); H01L 21/823814 (2013.01); H01L 21/823842 (2013.01); H01L 21/823871 (2013.01); H01L 23/5286 (2013.01); H01L 27/1104 (2013.01); H01L 27/1116 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/41733 (2013.01); H01L 29/41791 (2013.01); H01L 29/42392 (2013.01); H01L 29/4908 (2013.01); H01L 29/4966 (2013.01); H01L 29/66545 (2013.01); H01L 29/7851 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate;
an array of first SRAM cells over the substrate, wherein each of the first SRAM cells includes two first p-type FinFET transistors and four first n-type FinFET transistors, wherein each of the first p-type FinFET transistors and the first n-type FinFET transistors includes a transistor channel in a single semiconductor fin and two source/drain regions connected by the transistor channel, wherein the array of the first SRAM cells are arranged with a first X-pitch along a first direction and a first Y-pitch along a second direction perpendicular to the first direction; and
an array of second SRAM cells over the substrate, wherein each of the second SRAM cells includes two second p-type FinFET transistors and four second n-type FinFET transistors, wherein each of the second p-type FinFET transistors includes a transistor channel in a single semiconductor fin and two source/drain regions connected by the transistor channel, wherein each of the second n-type FinFET transistors includes a transistor channel in multiple semiconductor fins and two source/drain regions connected by the transistor channel, wherein the array of the second SRAM cells are arranged with a second X-pitch along the first direction and a second Y-pitch along the second direction,
wherein the source/drain regions of the first p-type FinFET transistors have a higher boron dopant concentration than the source/drain regions of the second p-type FinFET transistors, wherein a ratio of the second X-pitch to the first X-pitch is within a range of 1.1 to 1.5.