US 11,659,070 B2
Interface circuit for providing extension packet and processor including the same
Younho Jeon, Gimhae-si (KR); Hyeokjun Choe, Hwaseong-si (KR); and Jeongho Lee, Gwacheon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Sep. 3, 2021, as Appl. No. 17/466,742.
Claims priority of application No. 10-2020-0146196 (KR), filed on Nov. 4, 2020.
Prior Publication US 2022/0141322 A1, May 5, 2022
Int. Cl. H04L 69/22 (2022.01); H04L 69/04 (2022.01); H04L 69/08 (2022.01)
CPC H04L 69/22 (2013.01) [H04L 69/04 (2013.01); H04L 69/08 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An interface circuit comprising:
a packet transmitter configured to generate a plurality of transmission packets based on a request output from a core circuit, and to output the plurality of transmission packets, the plurality of transmission packets comprising information indicative of being a packet to be merged; and
a packet receiver configured to generate a merged packet by merging a plurality of extension packets from among a plurality of reception packets received from outside of the interface circuit, the plurality of extension packets comprising information indicative of being a packet to be merged,
wherein a sum of lengths of fields for processing the request is greater than a length of each of the plurality of transmission packets, and
wherein the packet transmitter is further configured to encode the plurality of transmission packets in different formats from each other such that the fields for the request are dispersed in the plurality of transmission packets.