US 11,658,685 B2
Memory with multi-mode ECC engine
Chin-Chu Chung, Hsinchu (TW); Chien-Hsin Liu, Hsinchu (TW); Hung-Jen Kao, Hsinchu (TW); and Yu-Chih Yeh, Hsinchu (TW)
Assigned to MACRONIX INTERNATIONAL CO., LTD., Hsinchu (TW)
Filed by MACRONIX INTERNATIONAL CO., LTD., Hsinchu (TW)
Filed on Oct. 5, 2021, as Appl. No. 17/494,361.
Prior Publication US 2023/0106125 A1, Apr. 6, 2023
Int. Cl. H03M 13/00 (2006.01); H03M 13/35 (2006.01); G06F 11/10 (2006.01)
CPC H03M 13/356 (2013.01) [G06F 11/1068 (2013.01)] 21 Claims
OG exemplary drawing
 
19. A method for operating a storage device in which error rates can depend on operating conditions, comprising:
identifying a portion of a memory array, and determining operating conditions of the identified portion;
selecting an error correcting code (ECC) algorithm from a plurality of ECC algorithms having different code rates, the ECC algorithm being selected in dependence on the identified portion and the determined operating conditions;
generating one or more codewords using the selected ECC algorithm for storage in the identified portion;
mapping portions of the memory array to the selected ECC algorithm in a table that maps different ECC algorithms to addresses of the memory array; and
writing the one or more codewords to the identified portion of the memory array according to the selected ECC algorithm.