US 11,658,675 B2
Successive-approximation register analog-to-digital converter, correction method and correction system
Shih-Lun Chen, Taoyuan (TW); Chun Kuan Wu, Taoyuan (TW); Chun Yu Lin, Taoyuan (TW); and Wen-Shen Lo, Taoyuan (TW)
Assigned to Chung Yuan Christian University, Taoyuan (TW)
Filed by Chung Yuan Christian University, Taoyuan (TW)
Filed on Nov. 22, 2021, as Appl. No. 17/533,030.
Claims priority of application No. 110137196 (TW), filed on Oct. 6, 2021.
Prior Publication US 2023/0108759 A1, Apr. 6, 2023
Int. Cl. H03M 1/40 (2006.01); H03M 1/10 (2006.01)
CPC H03M 1/403 (2013.01) [H03M 1/1023 (2013.01)] 11 Claims
OG exemplary drawing
1. A successive-approximation register analog-to-digital converter comprising:
a comparator;
a capacitor array coupled to an input terminal of the comparator, and comprising a plurality of capacitors corresponding to different bits;
a control circuit coupled to an output terminal of the comparator, and configured to store a plurality of original weight values corresponding to the capacitors; and
a processor coupled to the control circuit and the capacitor array, and configured to:
generate an original weight value sequence according to the original weight values,
control the control circuit, the capacitor array, and the comparator to convert an analog time-varying signal to establish a transforming curve corresponding to the original weight values,
generate an offset value sequence according to an offset of the transforming curve, and
use the offset value sequence to correct the original weight value sequence to generate a corrected weight value sequence, and provide a plurality of corrected weight values of the corrected weight value sequence to the control circuit.