US 11,658,674 B2
Analog-to-digital converter circuit, corresponding system and method
Nicola Errico, Rho (IT); Marzia Annovazzi, Milan (IT); Alessandro Cannone, Marsala (IT); Enrico Ferrara, Milan (IT); Gea Donzelli, Caronno Pertusella (IT); and Paolo Turbanti, Milan (IT)
Assigned to STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed by STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed on Oct. 14, 2021, as Appl. No. 17/501,112.
Claims priority of application No. 102020000026678 (IT), filed on Nov. 9, 2020.
Prior Publication US 2022/0149859 A1, May 12, 2022
Int. Cl. H03M 1/10 (2006.01); H03M 1/06 (2006.01)
CPC H03M 1/1071 (2013.01) [H03M 1/0687 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An electronic circuit comprising:
N sensing channels, each of the N sensing channels comprising a pair of sensing nodes comprising first and second sensing nodes, wherein N is a positive integer greater than 1;
N analog-to-digital converters, each of the N analog-to-digital converters having an input coupled to a respective first sensing node of the N sensing channels;
a first multiplexer having inputs respectively coupled to the second sensing nodes of N sensing channels;
a second multiplexer having inputs respectively coupled to outputs of the N analog-to-digital converters;
a further analog-to-digital converter having an input coupled to an output of the first multiplexer; and
an error checking circuit coupled to an output of the second multiplexer and to an output of the further analog-to-digital converter, wherein:
the first and second multiplexers are configured to operate over a sequence of N time windows and to apply to the error checking circuit, at each time window in the sequence of N time windows, a first digital value resulting from a conversion to digital of an analog sensing signal at a selected one of the respective first sensing nodes of the N sensing nodes and a second digital value resulting from a conversion to digital of an analog sensing signal at the second sensing node of the N second sensing nodes paired with the selected one of the respective first sensing nodes, and
the error checking circuit is configured to compare, at each time window in the sequence of N time windows, the first digital value and the second digital value and produce over the sequence of N time windows, N sensing error signals as a function of the difference between the first digital value and the second digital value.