US 11,658,671 B2
Latency reduction in analog-to-digital converter-based receiver circuits
Ryan D. Bartling, Sunnyvale, CA (US); Jafar Savoj, Sunnyvale, CA (US); Brian S. Leibowitz, San Francisco, CA (US); and Shah M. Sharif, San Jose, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Sep. 22, 2021, as Appl. No. 17/482,322.
Prior Publication US 2023/0093114 A1, Mar. 23, 2023
Int. Cl. H03M 1/00 (2006.01); H03M 1/06 (2006.01)
CPC H03M 1/0687 (2013.01) [H03M 1/0626 (2013.01); H03M 1/0648 (2013.01); H03M 1/0663 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a front-end circuit configured to generate an equalized signal using a plurality of signals that encode a serial data stream that includes a plurality of data symbols;
a sample circuit including a plurality of analog-to-digital converter circuits, wherein an activated subset of the plurality of analog-to-digital converter circuits are configured to sample, using a recovered clock signal, the equalized signal during respective time periods to generate corresponding sets of samples, wherein a number of analog-to-digital converter circuits included in the activated subset is based on a baud rate of the serial data stream, wherein the sample circuit is configured to generate a plurality of serialized sample streams that include samples from respective subsets of the activated subset of the plurality of analog-to-digital converter circuits, wherein a first serialized sample stream of the plurality of serialized sample streams includes first data corresponding to even-numbered data symbols of the plurality of data symbols, and wherein a second serialized sample stream of the plurality of serialized sample streams includes second data corresponding to odd-numbered data symbols of the plurality of data symbols; and
a recovery circuit configured to generate, using the corresponding sets of samples, the recovered clock signal and a plurality of recovered data symbols.