US 11,658,665 B2
Clock synchronization circuit, semiconductor device, and clock synchronization method
Daisuke Nihei, Kanagawa (JP)
Assigned to LAPIS TECHNOLOGY CO., LTD., Yokohama (JP)
Filed by LAPIS TECHNOLOGY CO., LTD., Kanagawa (JP)
Filed on Mar. 22, 2022, as Appl. No. 17/700,997.
Claims priority of application No. JP2021-060533 (JP), filed on Mar. 31, 2021.
Prior Publication US 2022/0321131 A1, Oct. 6, 2022
Int. Cl. H03L 7/00 (2006.01); H03K 19/20 (2006.01)
CPC H03L 7/00 (2013.01) [H03K 19/20 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A clock synchronization circuit comprising:
a signal generation circuit configured to generate a first signal and a second signal by receiving a signal output under a first clock with two logic circuits that respectively operate under a second clock that is different from the first clock; and
a synchronization circuit configured to:
receive the first signal, the second signal, and a synchronization enabling signal for adjusting phases of the first signal and the second signal, and
control the phases of the first signal and the second signal using a first output result from a logical operation performed on the second signal and on a result of a logical operation with the first signal and the synchronization enabling signal, and using a second output result from a logical operation performed on the first signal and on a result of a logical operation with the second signal and the synchronization enabling signal.