US 11,658,662 B2
Leakage current reduction in electronic devices
Hiroshi Akamatsu, Boise, ID (US); Ki-Jun Nam, Boise, ID (US); and John David Porter, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, inc., Boise, ID (US)
Filed on Oct. 23, 2020, as Appl. No. 17/78,965.
Application 17/078,965 is a continuation of application No. 16/205,953, filed on Nov. 30, 2018, granted, now 10,848,153.
Prior Publication US 2021/0044296 A1, Feb. 11, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 19/00 (2006.01); H03K 19/096 (2006.01)
CPC H03K 19/0016 (2013.01) [H03K 19/0963 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving an input signal at a first transistor and a second transistor;
applying a control signal to a gate of a third transistor that is coupled with the second transistor;
deactivating the input signal after applying the control signal;
adjusting a voltage of the control signal based at least in part on deactivating the input signal;
receiving an output signal at a fourth transistor and a sixth transistor;
applying, prior to deactivating the input signal, a second control signal to a gate of a fifth transistor that is coupled with the fourth transistor; and
adjusting a voltage of the second control signal based at least in part on deactivating the input signal.