US 11,658,656 B2
Low power clock gating cell and an integrated circuit including the same
Hyunchul Hwang, Suwon-si (KR); and Youngo Lee, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Nov. 1, 2021, as Appl. No. 17/515,607.
Claims priority of application No. 10-2020-0161569 (KR), filed on Nov. 26, 2020; application No. 10-2020-0166964 (KR), filed on Dec. 2, 2020; application No. 10-2021-0048027 (KR), filed on Apr. 13, 2021; and application No. 10-2021-0106184 (KR), filed on Aug. 11, 2021.
Prior Publication US 2022/0166427 A1, May 26, 2022
Int. Cl. H03K 17/687 (2006.01); H03K 3/356 (2006.01)
CPC H03K 17/6871 (2013.01) [H03K 3/356 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A clock gating cell, comprising:
a first circuit configured to receive an enable signal and an inverted output clock signal and generate a first signal through a first node;
a second circuit configured to receive the first signal and generate an inverted first signal;
a third circuit configured to receive the first signal, the inverted first signal, and an input clock signal, generate the first signal by being connected to the first circuit through the first node, and generate the inverted output clock signal through a second node; and
a fourth circuit configured to directly receive the first signal, generate the inverted output clock signal by being connected to the third circuit through the second node, and generate an output clock signal,
wherein the third circuit comprises a pair of transistors receiving the input clock signal.