US 11,658,653 B2
Gate resistance adjustment device
Kazuto Takao, Tsukuba (JP); and Yusuke Hayashi, Yokohama (JP)
Assigned to KABUSHIKI KAISHA TOSHIBA, Tokyo (JP)
Filed by KABUSHIKI KAISHA TOSHIBA, Tokyo (JP)
Filed on Apr. 12, 2021, as Appl. No. 17/228,093.
Application 17/228,093 is a division of application No. 16/564,580, filed on Sep. 9, 2019, granted, now 11,038,500.
Claims priority of application No. JP2019-000272 (JP), filed on Jan. 4, 2019.
Prior Publication US 2021/0234539 A1, Jul. 29, 2021
Int. Cl. H03K 17/082 (2006.01); H03K 17/687 (2006.01)
CPC H03K 17/0828 (2013.01) [H03K 17/687 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A gate resistance adjustment device comprising:
a noise simulation unit that simulates noise of a switching device and a peripheral circuit of the switching device;
a target waveform selection unit that selects a graphical waveform that is an imitation of a target waveform of at least one of a drain voltage or a collector voltage of the switching device and a drain current or a collector current of the switching device based on a result of a simulation in the noise simulation unit;
an extraction unit that extracts time required for at least one of turning on or off the switching device and a steady-state drain current or a steady-state collector current of the switching device based on the graphical waveform selected by the target waveform selection unit;
a calculator that calculates a gate resistance of the switching device based on the time and the steady-state drain current or the steady-state collector current that are extracted by the extraction unit; and
a setting unit that sets a gate resistance calculated by the calculator in the switching device.