US 11,658,648 B1
Variation tolerant linear phase-interpolator
Hyung-Joon Jeon, Irvine, CA (US); Yonghyun Shim, Irvine, CA (US); Delong Cui, Tustin, CA (US); and Jun Cao, Irvine, CA (US)
Assigned to Avago Technologies International Sales Pte. Limited, Singapore (SG)
Filed by Avago Technologies International Sales Pte. Limited, Singapore (SG)
Filed on Jan. 31, 2022, as Appl. No. 17/589,682.
Int. Cl. H03K 5/135 (2006.01); H03L 7/085 (2006.01); H03L 7/08 (2006.01); H03K 5/00 (2006.01)
CPC H03K 5/135 (2013.01) [H03L 7/085 (2013.01); H03K 2005/00052 (2013.01); H03L 7/0807 (2013.01)] 20 Claims
OG exemplary drawing
 
15. A system comprising:
a sampler configured to convert an input signal to a digital output signal;
a receiver phase-locked loop circuit configured to provide one or more input clock signals;
a phase interpolation circuit coupled to the receiver phase-locked loop circuit and the sampler, wherein the phase interpolation circuit is configured to provide a combined recovered clock signal to the sampler, wherein the phase interpolation circuit further comprises:
a first phase interpolator configured to generate a first recovered clock signal based on the one or more input clock signals and a first code; and
a second phase interpolator configured generate a second recovered clock signal based on the one or more input clock signals and a second code, wherein the second code has an interpolation code offset from the first code, wherein the interpolation code offset corresponds to a phase shift in the second recovered clock signal relative to the first recovered clock signal;
wherein the outputs of the first phase interpolator and second phase interpolator are configured to be merged, wherein when combined, the first and second recovered clock signals form a combined recovered clock signal.