US 11,658,481 B1
Source and drain enabled conduction triggers and immunity tolerance for integrated circuits
Stephen R. Fairbanks, Mesa, AZ (US)
Assigned to Amplexia, LLC, Durham, NC (US)
Filed by Amplexia, LLC, Durham, NC (US)
Filed on Jan. 14, 2022, as Appl. No. 17/576,267.
Application 17/576,267 is a continuation of application No. 16/883,431, filed on May 26, 2020, granted, now 11,228,174.
Claims priority of provisional application 62/854,670, filed on May 30, 2019.
This patent is subject to a terminal disclaimer.
Int. Cl. H02H 9/04 (2006.01); H01L 27/02 (2006.01)
CPC H02H 9/046 (2013.01) [H01L 27/0262 (2013.01); H01L 27/0266 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A method of designing an integrated circuit with enhanced EOS/ESD robustness, comprising the steps of:
(a) designing a plurality of input/output pads in the integrated circuit;
(b) designing a positive voltage rail in the integrated circuit;
(c) designing a ground voltage rail in the integrated circuit;
(d) designing a collection of internal circuits, in the integrated circuit, representing the operational core of the integrated circuit in the integrated circuit;
(e) designing a plurality of input/output buffering circuits, in the integrated circuit, connected as inputs and outputs to the internal circuits, wherein the internal circuits and the input/output buffering circuits comprise functional devices; and
(f) designing a plurality of EOS/ESD protection circuits, in the integrated circuit, interconnected with the input/output pads to limit ESD voltage and/or shunt ESD current away from the functional devices, wherein at least one of the EOS/ESD protection circuits is a MOSFET;
(g) wherein designing the MOSFET includes designing a source region of the MOSFET to have an accompanying ohmic contact and designing the MOSFET to have a rectifying junction contact in place of a drain region and accompanying ohmic contact of the MOSFET; and
(h) wherein the at least one EOS/ESD protection circuit has a first I-V characterization curve having a first snapback voltage, wherein at least one of the functional devices has a second I-V characterization curve having a second snapback voltage, and wherein the rectifying junction contact in the at least one EOS/ESD protection circuit causes the first snapback voltage to be less than the second snapback voltage.