US 11,658,248 B2
Flash memory device with three-dimensional half flash structure and methods for forming the same
Yu-Chu Lin, Tainan (TW); Chi-Chung Jen, Kaohsiung (TW); Yi-Ling Liu, Hsinchu (TW); Wen-Chih Chiang, Hsinchu (TW); Keng-Ying Liao, Tainan (TW); and Huai-jen Tung, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Mar. 3, 2021, as Appl. No. 17/191,334.
Prior Publication US 2022/0285558 A1, Sep. 8, 2022
Int. Cl. H10B 41/30 (2023.01); H10B 41/10 (2023.01); H01L 29/788 (2006.01); H01L 27/11521 (2017.01); H01L 29/423 (2006.01); H01L 29/417 (2006.01); H01L 21/265 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/7883 (2013.01) [H01L 21/26513 (2013.01); H01L 27/11521 (2013.01); H01L 29/40114 (2019.08); H01L 29/41725 (2013.01); H01L 29/42324 (2013.01); H01L 29/66492 (2013.01); H01L 29/66825 (2013.01); H01L 29/7833 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A flash memory cell located on a substrate comprising:
a source region and a drain region in the substrate;
a channel region in the substrate, extending in a first direction from the source region to the drain region;
a tunnel dielectric layer on the channel region;
a floating gate electrode on the tunnel dielectric layer;
a control gate dielectric layer on the floating gate electrode;
a smaller length control gate electrode on the control gate dielectric layer, wherein a length of the smaller length control gate electrode in the first direction is less than a length of the floating gate electrode in the first direction; and
a fourth electrical contact contacting the control gate dielectric layer over the channel region and including an outermost sidewall located opposite the smaller length control gate electrode and over the floating gate electrode.