US 11,658,236 B2
III-V semiconductor device with integrated power transistor and start-up circuit
Florin Udrea, Cambridge (GB); Loizos Efthymiou, Cambridge (GB); Giorgia Longobardi, Cambridge (GB); and Martin Arnold, Cambridge (GB)
Assigned to CAMBRIDGE GAN DEVICES LIMITED, Cambourne (GB)
Filed by Cambridge GaN Devices Limited, Cambourne (GB)
Filed on May 7, 2019, as Appl. No. 16/405,537.
Prior Publication US 2020/0357909 A1, Nov. 12, 2020
Int. Cl. H01L 29/778 (2006.01); H01L 27/095 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/66 (2006.01); H01L 27/02 (2006.01); H01L 27/06 (2006.01); H01L 27/07 (2006.01); H01L 27/088 (2006.01)
CPC H01L 29/7787 (2013.01) [H01L 27/027 (2013.01); H01L 27/0605 (2013.01); H01L 27/0738 (2013.01); H01L 27/088 (2013.01); H01L 27/095 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/66462 (2013.01); H01L 29/778 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A III-nitride semiconductor based heterojunction power device, comprising:
a first heterojunction transistor formed on a substrate, the first heterojunction transistor comprising:
a first III-nitride semiconductor region formed over the substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least a first two dimensional carrier gas of a second conductivity type;
a first terminal operatively connected to the first III-nitride semiconductor region;
a second terminal laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region;
a first highly doped semiconductor region of a first conductivity type formed over the first III-nitride semiconductor region, and between the first terminal and the second terminal;
a first gate region being formed over the first highly doped semiconductor region, and between the first terminal and the second terminal; and
a second heterojunction transistor formed on the substrate, the second heterojunction transistor comprising:
a second III-nitride semiconductor region formed over the substrate, wherein the second III-nitride semiconductor region comprises a second heterojunction comprising at least a second two dimensional carrier gas of the second conductivity type;
a third terminal operatively connected to the second III-nitride semiconductor region;
a fourth terminal operatively connected to the second III-nitride semiconductor region, wherein within an active area of the second heterojunction transistor the fourth terminal is laterally spaced from the third terminal in a first dimension;
a second plurality of highly doped semiconductor regions of the first conductivity type formed over the second III-nitride semiconductor region, the second plurality of highly doped semiconductor regions being formed between the third terminal and the fourth terminal, wherein the second plurality of highly doped semiconductor regions comprises at least two highly doped semiconductor regions of the first conductivity type in contact with the second III-nitride semiconductor region and laterally spaced from each other in a second dimension that is perpendicular to the first dimension;
a second gate region operatively connected to the first plurality of highly doped semiconductor regions, and
wherein one of the first heterojunction transistor and the second heterojunction transistor is an enhancement mode field effect transistor and the other one of the first heterojunction transistor and the second heterojunction transistor is a depletion mode field effect transistor.