US 11,658,208 B2
Thin film transistors for high voltage applications
Abhishek A. Sharma, Hillsboro, OR (US); Willy Rachmady, Beaverton, OR (US); Van H. Le, Beaverton, OR (US); Gilbert Dewey, Hillsboro, OR (US); and Ravi Pillarisetty, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 20, 2018, as Appl. No. 15/926,969.
Prior Publication US 2019/0296104 A1, Sep. 26, 2019
Int. Cl. H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/51 (2006.01); H01L 21/28 (2006.01); H01L 27/11573 (2017.01); H01L 29/792 (2006.01)
CPC H01L 29/0611 (2013.01) [H01L 29/517 (2013.01); H01L 29/66742 (2013.01); H01L 27/11573 (2013.01); H01L 29/40117 (2019.08); H01L 29/66833 (2013.01); H01L 29/792 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A thin film transistor (TFT) apparatus, comprising:
a gate comprising metal;
a source and a drain;
a semiconductor body;
a multilayer gate dielectric between the gate and the semiconductor body, the multilayer gate dielectric comprising a first layer, a second layer on the first layer, and a third layer on the second layer, the first layer comprising a first material, the second layer comprising a second material, and the third layer comprising the first material, wherein the first or second material comprises hafnium, zirconium, and oxygen, and the other of the first or second material comprises aluminum and oxygen;
wherein the source and drain are substantially coplanar, and wherein the source and drain are opposite the semiconductor body from the gate.