US 11,658,183 B2
Metallization structures under a semiconductor device layer
Aaron D. Lilak, Beaverton, OR (US); Rishabh Mehandru, Portland, OR (US); Patrick Morrow, Portland, OR (US); and Stephen M. Cea, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jul. 9, 2021, as Appl. No. 17/372,345.
Application 17/372,345 is a division of application No. 16/615,378, granted, now 11,107,811, previously published as PCT/US2017/040549, filed on Jul. 1, 2017.
Prior Publication US 2021/0343710 A1, Nov. 4, 2021
Int. Cl. H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 27/06 (2006.01); H01L 29/78 (2006.01)
CPC H01L 27/0886 (2013.01) [H01L 21/823431 (2013.01); H01L 23/528 (2013.01); H01L 23/53228 (2013.01); H01L 27/0688 (2013.01); H01L 29/785 (2013.01)] 13 Claims
OG exemplary drawing
1. A method of fabricating a transistor structure, the method comprising:
forming features comprising a semiconductor material and separated by isolation, the isolation comprising a dielectric material, and the features having tops opposite bottoms with sidewalls therebetween;
forming one or more transistor terminals over the tops or the sidewalls of one or more of the features;
forming trenches self-aligned to the features by recessing the bottoms of the features selectively to the isolation or by recessing the isolation relative to the bottoms of the features;
forming metallization structures by at least partially backfilling the trenches with a metal, wherein the metallization structures are in contact with the bottoms of the features or with the isolation, and wherein individual ones of the metallization structures are separated by either the isolation or the features.