US 11,658,172 B2
Hybrid bonding with through substrate via (TSV)
Jing-Cheng Lin, Zhudong Township, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Sep. 27, 2019, as Appl. No. 16/585,868.
Application 15/997,156 is a division of application No. 14/752,342, filed on Jun. 26, 2015, granted, now 9,991,244, issued on Jun. 5, 2018.
Application 14/752,342 is a division of application No. 13/943,224, filed on Jul. 16, 2013, granted, now 9,087,821, issued on Jul. 21, 2015.
Application 16/585,868 is a continuation of application No. 15/997,156, filed on Jun. 4, 2018, granted, now 10,461,069.
Prior Publication US 2020/0027868 A1, Jan. 23, 2020
Int. Cl. H01L 23/48 (2006.01); H01L 25/00 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 25/50 (2013.01) [H01L 21/76895 (2013.01); H01L 21/76897 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 24/89 (2013.01); H01L 25/0657 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/02372 (2013.01); H01L 2224/05024 (2013.01); H01L 2224/0569 (2013.01); H01L 2224/05547 (2013.01); H01L 2224/05576 (2013.01); H01L 2224/05582 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/09181 (2013.01); H01L 2224/80075 (2013.01); H01L 2224/80097 (2013.01); H01L 2224/80121 (2013.01); H01L 2224/80204 (2013.01); H01L 2224/80815 (2013.01); H01L 2224/80855 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2224/80986 (2013.01); H01L 2224/9202 (2013.01); H01L 2224/94 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06527 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06558 (2013.01); H01L 2924/0002 (2013.01); H01L 2924/1304 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device structure, comprising:
a first polymer layer formed between a first substrate and a second substrate;
a first gate electrode formed below the first substrate;
a first contact plug formed below the first gate electrode;
a first conductive layer formed over the first polymer, wherein the first conductive layer is directly below the first gate electrode; and
a first through substrate via (TSV) formed over the first conductive layer, wherein the first conductive layer has a first surface and an opposite second surface, the first surface is in direct contact with the first TSV and the opposite second surface is in direct contact with the first polymer, and an upper surface and a lower surface of the first contact plug that are in direct contact with the first gate electrode and the first surface of the first conductive layer respectively; and
a second TSV formed entirely through the second substrate, wherein the first maximum height of the first TSV is smaller than a second maximum height of the second TSV.