US 11,658,171 B2
Dual cool power module with stress buffer layer
Jonghwan Baek, Bucheon (KR); JeongHyuk Park, Incheon (KR); Seungwon Im, Seoul (KR); and Keunhyuk Lee, Suzhou (CN)
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed by SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Phoenix, AZ (US)
Filed on Dec. 23, 2020, as Appl. No. 17/247,797.
Prior Publication US 2022/0199602 A1, Jun. 23, 2022
Int. Cl. H01L 23/495 (2006.01); H01L 25/18 (2023.01); H01L 23/367 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/18 (2013.01) [H01L 23/3107 (2013.01); H01L 23/3677 (2013.01); H01L 23/49524 (2013.01); H01L 23/49575 (2013.01); H01L 24/32 (2013.01); H01L 24/33 (2013.01); H01L 25/50 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/33181 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A semiconductor device package, comprising:
a leadframe;
a direct bonded metal (DBM) substrate connected to the leadframe;
a first semiconductor die disposed on a patterned metal layer of the direct bonded metal (DBM) substrate;
a second semiconductor die disposed on the patterned metal layer of the direct bonded metal (DBM) substrate;
a clip electrically connected to the first semiconductor die and the second semiconductor die;
an electrically-isolating stress buffer layer disposed on the clip;
a heatsink disposed on the clip with the stress buffer layer disposed therebetween; and
a mold material encapsulating the first semiconductor die, the second semiconductor die, the clip, and the stress buffer layer, and partially encapsulating the leadframe, the DBM substrate, and the heatsink,
wherein the first semiconductor die is flip-attached to the patterned metal layer of the DBM substrate, and the first semiconductor die, the clip, and the second semiconductor die are connected in series.