US 11,658,159 B2
Methods and apparatus for managing thermal behavior in multichip packages
Saravanan Sethuraman, Palau Pinang (MY); Tonia Morris, Wendell, NC (US); Siaw Kang Lai, Penang (MY); Yee Choong Lim, Penang (MY); and Yu Ying Ong, Penang (MY)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 24, 2021, as Appl. No. 17/485,078.
Application 17/485,078 is a continuation of application No. 16/701,739, filed on Dec. 3, 2019, granted, now 11,164,847.
Prior Publication US 2022/0013505 A1, Jan. 13, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/00 (2006.01); H01L 25/065 (2023.01); G11C 5/02 (2006.01); G06F 12/10 (2016.01)
CPC H01L 25/0657 (2013.01) [G06F 12/10 (2013.01); G11C 5/025 (2013.01); G06F 2212/657 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06589 (2013.01)] 20 Claims
OG exemplary drawing
20. A system, comprising:
a package substrate;
an interposer on the package substrate;
a memory stack that includes multiple vertically stacked dies mounted on the interposer; and
a main die that is mounted on the interposer and that comprises switching circuitry configurable to selectively access different dies of the memory stack based at least in part on a bandwidth utilization metric and a temperature of the vertically stacked dies in the memory stack.