US 11,658,158 B2
Die to die interface circuit
Tze-Chiang Huang, Saratoga, CA (US); King-Ho Tam, Hsinchu County (TW); and Yu-Hao Liu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu (TW)
Filed on Jun. 30, 2021, as Appl. No. 17/363,121.
Claims priority of provisional application 63/074,153, filed on Sep. 3, 2020.
Prior Publication US 2022/0068888 A1, Mar. 3, 2022
Int. Cl. H01L 25/065 (2023.01); H01L 23/528 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 23/5286 (2013.01); H01L 25/50 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06544 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a first die; and
a second die disposed above the first die along a direction, the second die including:
a first layer,
a second layer disposed above the first layer along the direction,
a first metal rail extending through the first layer along the direction to electrically couple to the first die,
a second metal rail extending through the second layer along the direction, and
a first interface circuit disposed in the second layer, the first interface circuit to propagate a signal between the first metal rail and the second metal rail, while electrically separating between an electrical load of the first metal rail and an electrical load of the second metal rail.