US 11,658,157 B2
Integrated circuit including a first semiconductor wafer and a second semiconductor wafer, semiconductor device including a first semiconductor wafer and a second semiconductor wafer and method of manufacturing same
Chih-Lin Chen, Hsinchu (TW); Hui-Yu Lee, Hsinchu (TW); Fong-Yuan Chang, Hsinchu (TW); Po-Hsiang Huang, Hsinchu (TW); and Chin-Chou Liu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jun. 10, 2021, as Appl. No. 17/344,318.
Application 17/344,318 is a continuation of application No. 16/718,352, filed on Dec. 18, 2019, granted, now 11,043,473.
Application 16/718,352 is a continuation of application No. 16/009,579, filed on Jun. 15, 2018, granted, now 10,535,635, issued on Jan. 14, 2020.
Prior Publication US 2021/0305213 A1, Sep. 30, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 25/065 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/538 (2006.01); H01L 49/02 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 23/528 (2013.01); H01L 23/5227 (2013.01); H01L 23/5389 (2013.01); H01L 24/32 (2013.01); H01L 24/83 (2013.01); H01L 25/50 (2013.01); H01L 28/10 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/83896 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06531 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/1206 (2013.01); H01L 2924/19042 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a first semiconductor wafer having a first device in a first side of the first semiconductor wafer;
a second semiconductor wafer over the first semiconductor wafer;
a first interconnect structure on a second side of the first semiconductor wafer opposite from the first side of the first semiconductor wafer;
an inductor below the first semiconductor wafer, and at least a portion of the inductor being within the first interconnect structure; and
a through substrate via extending through the first semiconductor wafer, and the inductor being coupled to at least the first device by at least the through substrate via.