US 11,658,148 B2
Semiconductor package and a method for manufacturing the same
Hyuekjae Lee, Hwaseong-si (KR); Jihoon Kim, Asan-si (KR); JiHwan Suh, Suwon-si (KR); So Youn Lee, Hwaseong-si (KR); Jihwan Hwang, Hwaseong-si (KR); Taehun Kim, Asan-si (KR); and Ji-Seok Hong, Yongin-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Apr. 21, 2020, as Appl. No. 16/854,452.
Claims priority of application No. 10-2019-0089968 (KR), filed on Jul. 25, 2019.
Prior Publication US 2021/0028146 A1, Jan. 28, 2021
Int. Cl. H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 25/18 (2023.01); H01L 21/56 (2006.01)
CPC H01L 25/0652 (2013.01) [H01L 21/565 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2224/08146 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06555 (2013.01); H01L 2225/06586 (2013.01); H01L 2225/06589 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a substrate;
a first semiconductor chip on the substrate;
a second semiconductor chip on the first semiconductor chip so that the first semiconductor chip is vertically between the second semiconductor chip and the substrate;
a first molding layer adjacent to a sidewall of the first semiconductor chip on the substrate, the first molding layer formed of a first molding material; and
a second molding layer adjacent to a sidewall of the second semiconductor chip on the substrate so that the first molding layer is vertically between the second molding layer and the substrate, the second molding layer formed of a second molding material different from the first molding material and having a bottom surface that is planar and contacts a planar top surface of the first molding material,
wherein a top surface of the first semiconductor chip and a top surface of the first molding layer are flat and are coplanar with each other,
wherein a ratio of the difference between the coefficient of thermal expansion between the second molding layer and the first molding layer to the difference between the coefficient of thermal expansion between the second molding layer and the substrate is between 5:1 and 20:1,
wherein the first semiconductor chip comprises: a first redistribution layer including a first chip pad provided at one surface of the first semiconductor chip; and a first through-electrode vertically penetrating the first semiconductor chip so as to be connected to the first chip pad through the first redistribution layer,
wherein the second semiconductor chip comprises: a second redistribution layer including a second chip pad provided at one surface of the second semiconductor chip; and a second through-electrode vertically penetrating the second semiconductor chip so as to be connected to the second chip pad through the second redistribution layer, and
wherein the first through-electrode and the second chip pad are bonded by hybrid bonding and constitute a single body formed of the same material at an interface of the first semiconductor chip and the second semiconductor chip.