US 11,658,144 B2
Innovative interconnect design for package architecture to improve latency
Md Altaf Hossain, Portland, OR (US); Ankireddy Nalamalpu, Portland, OR (US); and Dheeraj Subbareddy, Santa Clara, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 3, 2021, as Appl. No. 17/466,396.
Application 17/466,396 is a continuation of application No. 16/023,846, filed on Jun. 29, 2018, granted, now 11,121,109.
Claims priority of provisional application 62/577,581, filed on Oct. 26, 2017.
Prior Publication US 2022/0059491 A1, Feb. 24, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/14 (2006.01); H01L 23/00 (2006.01); G06F 13/38 (2006.01); H01L 25/065 (2023.01); G06F 13/42 (2006.01)
CPC H01L 24/18 (2013.01) [G06F 13/14 (2013.01); G06F 13/385 (2013.01); G06F 13/4221 (2013.01); G06F 13/4265 (2013.01); H01L 25/0652 (2013.01); H01L 25/0655 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit package comprising:
a package substrate comprising an interconnect bridge, a first electrical trace, and a second electrical trace, wherein the first and second electrical traces are located in the interconnect bridge;
a first die, mounted on the package substrate, and comprising a first input-output (IO) package connector and a second IO package connector that have a first pitch; and
a second die, mounted on the package substrate, and comprising a third IO package connector and a fourth IO package connector that have a second pitch, wherein the first and second pitches are different pitches, wherein the first electrical trace couples the first and the third IO package connectors, and wherein the second electrical trace couples the second and the fourth IO package connectors.