US 11,658,139 B2
Semiconductor package for improving bonding reliability
Jaehyung Park, Anyang-si (KR); Seokho Kim, Hwaseong-si (KR); Hoonjoo Na, Seoul (KR); Seongmin Son, Hwaseong-si (KR); Kyuha Lee, Seongnam-si (KR); and Yikoan Hong, Yongin-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Mar. 19, 2021, as Appl. No. 17/206,337.
Claims priority of application No. 10-2020-0094794 (KR), filed on Jul. 29, 2020.
Prior Publication US 2022/0037273 A1, Feb. 3, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01)
CPC H01L 24/06 (2013.01) [H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 24/32 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2224/05013 (2013.01); H01L 2224/05014 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/05139 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05157 (2013.01); H01L 2224/05176 (2013.01); H01L 2224/05554 (2013.01); H01L 2224/05562 (2013.01); H01L 2224/05564 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05638 (2013.01); H01L 2224/05649 (2013.01); H01L 2224/05666 (2013.01); H01L 2224/0603 (2013.01); H01L 2224/06051 (2013.01); H01L 2224/06131 (2013.01); H01L 2224/06135 (2013.01); H01L 2224/06136 (2013.01); H01L 2224/06177 (2013.01); H01L 2224/06505 (2013.01); H01L 2224/06517 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/32145 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a first semiconductor chip;
a second semiconductor chip arranged above the first semiconductor chip; and
main pad structures and dummy pad structures between the first semiconductor chip and the second semiconductor chip,
wherein the main pad structures comprise first main pad structures apart from one another on the first semiconductor chip and second main pad structures apart from one another on the second semiconductor chip and bonded to the first main pad structures,
wherein the dummy pad structures comprise first dummy pad structures comprising first dummy pads that are arranged apart from one another on the first semiconductor chip and first dummy capping layers arranged on the first dummy pads, and second dummy pad structures comprising second dummy pads that are arranged apart from one another on the second semiconductor chip and second dummy capping layers arranged on the second dummy pads, and
wherein the first dummy capping layers of the first dummy pad structures are not bonded to the second dummy capping layers of the second dummy pad structures.