US 11,658,132 B2
Integrated assemblies
Rohit Kothari, Boise, ID (US); Lifang Xu, Boise, ID (US); and Jian Li, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 22, 2021, as Appl. No. 17/559,321.
Application 17/559,321 is a continuation of application No. 16/662,705, filed on Oct. 24, 2019, granted, now 11,239,181.
Prior Publication US 2022/0115335 A1, Apr. 14, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 27/11519 (2017.01); H01L 27/11524 (2017.01); H01L 27/11582 (2017.01); H01L 27/11556 (2017.01); H01L 27/11565 (2017.01); H01L 27/1157 (2017.01); H01L 27/11573 (2017.01); H01L 27/11529 (2017.01); H01L 23/00 (2006.01)
CPC H01L 23/562 (2013.01) [H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 27/1157 (2013.01); H01L 27/11519 (2013.01); H01L 27/11524 (2013.01); H01L 27/11529 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01); H01L 27/11573 (2013.01); H01L 27/11582 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An integrated assembly comprising:
a memory array region extending across a portion of a die and comprising a stack of alternating insulative and conductive levels; the stack generating bending stresses on the die; and
one or more stress-moderating regions extending through the stack and configured to alleviate the bending stresses; the one or more stress-moderating regions together having an area which is at least about 5% of the total area of the memory array region.