US 11,658,119 B2
Backside signal interconnection
Yu-Xuan Huang, Hsinchu (TW); Ching-Wei Tsai, Hsinchu (TW); Yi-Hsun Chiu, Hsinchu County (TW); Yi-Bo Liao, Hsinchu (TW); Kuan-Lun Cheng, Hsin-Chu (TW); Wei-Cheng Lin, Taichung (TW); Wei-An Lai, Hsinchu (TW); Ming Chian Tsai, Hsinchu (TW); Jiann-Tyng Tzeng, Hsin Chu (TW); Hou-Yu Chen, Hsinchu County (TW); Chun-Yuan Chen, Hsinchu (TW); and Huan-Chieh Su, Changhua County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Mar. 9, 2021, as Appl. No. 17/196,174.
Claims priority of provisional application 63/106,264, filed on Oct. 27, 2020.
Prior Publication US 2022/0130759 A1, Apr. 28, 2022
Int. Cl. H01L 23/528 (2006.01); H01L 21/768 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 27/088 (2006.01); H01L 23/522 (2006.01)
CPC H01L 23/5286 (2013.01) [H01L 21/76838 (2013.01); H01L 23/5226 (2013.01); H01L 27/088 (2013.01); H01L 29/0649 (2013.01); H01L 29/78 (2013.01)] 20 Claims
OG exemplary drawing
 
14. A method, comprising:
providing a structure having first and second transistors wherein the first transistor includes a first source/drain (S/D) feature and the second transistor includes a second S/D feature, the structure further having a multi-layer interconnect over a frontside of the first and the second transistors, a first via disposed on a backside of the first S/D feature, a first semiconductor fin below the first S/D feature and adjacent to the first via, a second via disposed on a backside of the second S/D feature, a second semiconductor fin below the second S/D feature and adjacent to the second via, and a first isolation feature disposed on a backside of the structure, adjacent to the first and the second vias, and separating the first semiconductor fin from the second semiconductor fin;
partially removing the first isolation feature, thereby forming a trench at the backside of the structure, wherein the trench exposes a first sidewall surface of the first via, a second sidewall surface of the second via, a third sidewall surface of the first semiconductor fin, and a fourth sidewall surface of the second semiconductor fin;
depositing a dielectric spacer on surfaces of the trench;
patterning the dielectric spacer to expose the first sidewall surface and the second sidewall surface, resulting in a patterned dielectric spacer partially covering the third and the fourth sidewall surfaces;
depositing one or more metallic materials over the patterned dielectric spacer and filling the trench;
etching back the one or more metallic materials, the first via, and the second via, wherein a remaining portion of the one or more metallic materials electrically connects the first via and the second via; and
recessing the patterned dielectric spacer.