US 11,658,117 B2
Semiconductor devices having improved electrical characteristics and methods of fabricating the same
Taejin Park, Yongin-si (KR); Keunnam Kim, Yongin-si (KR); Sohyun Park, Seoul (KR); Jin-Hwan Chun, Seongnam-si (KR); Wooyoung Choi, Seoul (KR); Sunghee Han, Hwaseong-si (KR); Inkyoung Heo, Hwaseong-si (KR); and Yoosang Hwang, Yongin-si (KR)
Assigned to Samsung Electronics Co., Ltd.
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Feb. 9, 2022, as Appl. No. 17/667,866.
Application 17/667,866 is a continuation of application No. 16/879,009, filed on May 20, 2020, granted, now 11,282,787.
Claims priority of application No. 10-2019-0113475 (KR), filed on Sep. 16, 2019.
Prior Publication US 2022/0165657 A1, May 26, 2022
Int. Cl. H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 23/528 (2006.01); H01L 29/06 (2006.01); G11C 5/10 (2006.01); H01L 29/423 (2006.01); H01L 27/108 (2006.01); H01L 21/768 (2006.01)
CPC H01L 23/528 (2013.01) [G11C 5/10 (2013.01); H01L 21/76831 (2013.01); H01L 27/10888 (2013.01); H01L 29/0649 (2013.01); H01L 29/4236 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of fabricating a semiconductor device, the method comprising:
forming, on a substrate, a device isolation layer that defines a plurality of active regions;
forming a plurality of word lines on the substrate;
forming a first contact hole by etching a portion of the substrate;
forming a contact pattern and a conductive layer on the contact pattern, wherein the contact pattern is within the first contact hole;
forming a plurality of bit-line structures by etching the contact pattern and the conductive layer;
forming a second contact hole by etching the active regions between the bit-line structures;
forming a first buried contact in a lower portion of the second contact hole;
forming a plurality of spacer structures that cover sidewalls of the bit-line structures; and
forming a second buried contact between the spacer structures,
wherein the forming of the spacer structures comprises:
forming a first spacer that covers each of the sidewalls of the bit-line structures;
forming a second spacer that covers a sidewall of the first spacer; and
forming a third spacer that covers a sidewall of the second spacer, and
wherein the second spacer is in contact with a portion of an outer wall of the device isolation layer.