US 11,658,103 B2
Capacitor interposer layer (CIL) chiplet design with conformal die edge pattern around bumps
Je-Hsiung Lan, San Diego, CA (US); Jonghae Kim, San Diego, CA (US); and Jinseong Kim, Escondido, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on May 18, 2021, as Appl. No. 17/323,249.
Claims priority of provisional application 63/077,533, filed on Sep. 11, 2020.
Prior Publication US 2022/0084922 A1, Mar. 17, 2022
Int. Cl. H01L 21/00 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/64 (2006.01)
CPC H01L 23/49816 (2013.01) [H01L 21/486 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 23/49822 (2013.01); H01L 23/49833 (2013.01); H01L 23/49838 (2013.01); H01L 23/642 (2013.01)] 20 Claims
OG exemplary drawing
1. An integrated circuit (IC) package, comprising:
a chip having a front-side surface and a backside surface, opposite the front-side surface, the front-side surface having a plurality of bump sites; and
a plurality of dies, each of the plurality of dies comprising integrated passive devices, the plurality of dies having conformal non-rectangular die edge patterns to enable placement of a front-side surface of each of the plurality of dies on predetermined portions of the plurality of bumps sites on the front-side surface of the chip.