US 11,658,095 B2
Bump integrated thermoelectric cooler
Kelly Lofgreen, Phoenix, AZ (US); Chandra Mohan Jha, Chandler, AZ (US); and Krishna Vasanth Valavala, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 29, 2019, as Appl. No. 16/370,703.
Prior Publication US 2020/0312742 A1, Oct. 1, 2020
Int. Cl. H01L 23/38 (2006.01); H01L 23/48 (2006.01); H01L 23/00 (2006.01); H01L 25/18 (2023.01); H10N 10/82 (2023.01); H10N 10/01 (2023.01)
CPC H01L 23/38 (2013.01) [H01L 23/481 (2013.01); H01L 24/09 (2013.01); H01L 24/17 (2013.01); H01L 25/18 (2013.01); H10N 10/01 (2023.02); H10N 10/82 (2023.02); H01L 2924/1434 (2013.01)] 15 Claims
OG exemplary drawing
1. An IC package, comprising:
a first IC component comprising a plurality of first interconnects on a first surface of an IC die;
a second IC component comprising a plurality of second interconnects on a second surface thereof, wherein the second surface is opposite the first surface and wherein the second IC component is electrically coupled to the first IC component through a plurality of electrically conductive joints between the first interconnects and the second interconnects; and
a thermoelectric cooling (TEC) device between the first surface and the second surface and laterally adjacent to the joints, wherein the TEC device comprises a thermoelectric material that has a first interface with a first trace on the first IC component.