US 11,658,092 B2
Thermal interconnect structure for thermal management of electrical interconnect structure
Shao-Kuan Lee, Kaohsiung (TW); Cherng-Shiaw Tsai, New Taipei (TW); Ting-Ya Lo, Hsinchu (TW); Cheng-Chin Lee, Taipei (TW); Chi-Lin Teng, Taichung (TW); Kai-Fang Cheng, Taoyuan (TW); Hsin-Yen Huang, New Taipei (TW); Hsiao-Kang Chang, Hsinchu (TW); and Shau-Lin Shue, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Nov. 13, 2020, as Appl. No. 17/97,441.
Prior Publication US 2022/0157690 A1, May 19, 2022
Int. Cl. H01L 23/373 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 23/367 (2006.01)
CPC H01L 23/373 (2013.01) [H01L 21/7682 (2013.01); H01L 21/76877 (2013.01); H01L 23/481 (2013.01); H01L 23/53295 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated chip comprising:
an electrical interconnect structure arranged over a semiconductor substrate and comprising interconnect vias and interconnect wires embedded within interconnect dielectric layers;
a thermal interconnect structure arranged over the semiconductor substrate, arranged beside the electrical interconnect structure, and comprising thermal vias, thermal wires, and/or thermal layers, wherein the thermal interconnect structure is embedded within the interconnect dielectric layers; and
a thermal passivation layer arranged over a topmost one of the interconnect dielectric layers,
wherein the thermal interconnect structure has a higher thermal conductivity than the interconnect dielectric layers, and wherein a first one of the interconnect vias extends through a first one of the thermal layers and a first one of the interconnect dielectric layers to directly contact a first one of the interconnect wires.