US 11,658,085 B2
Integrated circuit package and method
Chien-Hsun Chen, Zhutian Township (TW); Yu-Ling Tsai, Hsinchu (TW); Jiun Yi Wu, Zhongli (TW); Chien-Hsun Lee, Chu-tung Town (TW); and Chung-Shi Liu, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 3, 2022, as Appl. No. 17/567,519.
Application 17/567,519 is a continuation of application No. 16/882,995, filed on May 26, 2020, granted, now 11,217,497.
Application 16/882,995 is a continuation of application No. 16/173,488, filed on Oct. 29, 2018, granted, now 10,665,520, issued on May 26, 2020.
Prior Publication US 2022/0122897 A1, Apr. 21, 2022
Int. Cl. H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 23/498 (2006.01)
CPC H01L 23/3121 (2013.01) [H01L 23/49827 (2013.01); H01L 23/5384 (2013.01)] 20 Claims
OG exemplary drawing
1. A device comprising:
a first integrated circuit die comprising first die connectors, the first die connectors disposed in a first contact region of the first integrated circuit die, a first edge region of the first integrated circuit die being free from die connectors;
an encapsulant encapsulating the first integrated circuit die;
a dielectric layer on the encapsulant; and
a metallization pattern comprising:
a first conductive via extending through the dielectric layer to contact one of the first die connectors, the first conductive via disposed in the first contact region; and
a conductive line extending along the dielectric layer, the conductive line having a first meandering portion and a straight portion, the first meandering portion disposed in the first edge region, the straight portion extending above the encapsulant, the first meandering portion connecting the straight portion to the first conductive via.