US 11,658,075 B2
Semiconductor device
Sangmin Yoo, Suwon-si (KR); Juyoun Kim, Suwon-si (KR); Hyungjoo Na, Seoul (KR); Bongseok Suh, Seoul (KR); Jooho Jung, Suwon-si (KR); Euichul Hwang, Seoul (KR); and Sungmoon Lee, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on May 3, 2021, as Appl. No. 17/246,778.
Application 17/246,778 is a continuation of application No. 16/408,912, filed on May 10, 2019, granted, now 11,062,961.
Claims priority of application No. 10-2018-0117040 (KR), filed on Oct. 1, 2018.
Prior Publication US 2021/0257264 A1, Aug. 19, 2021
Int. Cl. H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 23/522 (2006.01); H01L 29/06 (2006.01); H01L 21/311 (2006.01); H01L 21/8238 (2006.01); H01L 27/118 (2006.01); H01L 21/762 (2006.01)
CPC H01L 21/823878 (2013.01) [H01L 21/76224 (2013.01); H01L 27/11807 (2013.01); H01L 2027/11816 (2013.01); H01L 2027/11829 (2013.01); H01L 2027/11861 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate including an active pattern, the active pattern including a plurality of source/drain patterns in an upper portion thereof;
a gate electrode extending in a first direction and crossing the active pattern which extends in a second direction;
a pair of first gate spacers on opposite sidewalls of the gate electrode, respectively;
a separation structure extending in the first direction through the active pattern, the separation structure bisecting the active pattern;
a pair of second gate spacers on opposite sidewalls of the separation structure, respectively;
a first gate dielectric pattern between the gate electrode and the pair of first gate spacers;
a first gate capping pattern covering a top surface of the gate electrode; and
a plurality of active contacts connected to the plurality of source/drain patterns, respectively,
wherein the separation structure has a round bottom surface that is lower than bottom surfaces of the plurality of source/drain patterns,
wherein the separation structure comprises a first insulating layer, a second insulating layer on the first insulating layer, and a third insulating layer on the second insulating layer,
wherein the first insulating layer extends from the pair of second gate spacers toward the round bottom surface, and
wherein a bottom surface of the second insulating layer and a bottom surface of the third insulating layer are in direct contact with the substrate.