US 11,658,069 B2
Method for manufacturing a semiconductor device having an interconnect structure over a substrate
Ming-Fa Chen, Taichung (TW); Tzuan-Horng Liu, Longtan Township (TW); and Chao-Wen Shih, Zhubei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Sep. 4, 2020, as Appl. No. 17/12,312.
Claims priority of provisional application 63/000,404, filed on Mar. 26, 2020.
Prior Publication US 2021/0305094 A1, Sep. 30, 2021
Int. Cl. H01L 21/768 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 21/3065 (2006.01)
CPC H01L 21/76898 (2013.01) [H01L 21/76805 (2013.01); H01L 21/76831 (2013.01); H01L 21/76832 (2013.01); H01L 24/08 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/32 (2013.01); H01L 24/83 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 21/30655 (2013.01); H01L 21/76814 (2013.01); H01L 2224/02311 (2013.01); H01L 2224/02313 (2013.01); H01L 2224/02372 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/08225 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/8083 (2013.01); H01L 2224/83896 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06544 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a first interconnect structure over a first substrate, the first interconnect structure comprising dielectric layers and metallization patterns therein;
patterning the first interconnect structure to form a first opening exposing a portion of the first substrate;
coating the first opening with a barrier layer;
etching a second opening through the barrier layer and the exposed portion of the first substrate;
depositing a liner in the first opening and the second opening, the liner physically contacting the barrier layer;
filling the first opening and the second opening with a conductive material;
thinning the first substrate to expose a portion of the conductive material in the second opening, the conductive material extending through the first interconnect structure and the first substrate forming a through substrate via;
forming a second interconnect structure over the first interconnect structure and the through substrate via, the second interconnect structure comprising dielectric layers and metallization patterns therein, the metallization patterns of the second interconnect structure being electrically coupled to the metallization patterns of the first interconnect structure and to the through substrate via;
forming a first dielectric layer over the second interconnect structure; and
forming first bond pads in the first dielectric layer, the first bond pads being electrically coupled to the metallization patterns of the second interconnect structure.